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integrated circuit systems, inc. ICS951411 0891e?03/07/05 pin configuration recommended application: ati rs400 systems using intel p4 tm processors output features: 6 - pairs of src/pci-express clocks 2 - pairs of atig (src/pci express*) clocks 3 - pairs of intel p4 clocks 3 - 14.318 mhz ref clocks 1 - 48mhz usb clock 1 - 33 mhz pci clock seed key specifications: cpu outputs cycle-cycle jitter < 85ps src output cycle-cycle jitter <125ps pci outputs cycle-cycle jitter < 250ps +/- 300ppm frequency accuracy on cpu & src clocks system clock chip for ati rs400 p4 tm -based systems features/benefits: 2- programmable clock request pins for src clocks supports ck410 or ck409 frequency table mapping spread spectrum for emi reduction outputs may be disabled via smbus external crystal load capacitors for maximum frequency accuracy 56-pin ssop & tssop *other names and brands may be claimed as the property of others. functionality - (ck410# = 0) fs_c 1 fs_b 1 fs_a 1 cpu mhz src mhz pci mhz ref mhz u sb mhz 0 266.66 100.00 33.33 14.318 48.000 1 133.33 100.00 33.33 14.318 48.000 0 200.00 100.00 33.33 14.318 48.000 1 166.66 100.00 33.33 14.318 48.000 0 333.33 100.00 33.33 14.318 48.000 1 100.00 100.00 33.33 14.318 48.000 0 400.00 100.00 33.33 14.318 48.000 1 14.318 48.000 functionality - (ck410# = 1) fs_c 1 byte6 bit5 fs_b 1 fs_a 1 cpu mhz src mhz pci mhz ref mhz u sb mhz 00 100.00 100.00 33.33 14.318 48.000 10 200.00 100.00 33.33 14.318 48.000 01 133.33 100.00 33.33 14.318 48.000 11 166.67 100.00 33.33 14.318 48.000 00 200.00 100.00 33.33 14.318 48.000 10 400.00 100.00 33.33 14.318 48.000 01 266.67 100.00 33.33 14.318 48.000 11 333.33 100.00 33.33 14.318 48.000 1. fs_c, fs_b and fs_a are low-threshold inputs. please see the v il_fs and v ih_fs specifications in the input/supply/common output parameters table for correct values. reserved 1 0 0 0 1 1 0 1 x1 1 56 vddref x2 2 55 gnd vdd48 3 54 **fs_a/ref0 usb_48mhz 4 53 **fs_b/ref1 gnd 5 52 **test_sel/ref2 vtt_pwrgd#/pd 6 51 vddpci sclk 7 50 **ck410#/pciclk0 sdata 8 49 gndpci **fs_c 9 48 *cpu_stop# **clkreqa# 10 47 cpuclkt0 **clkreqb# 11 46 cpuclkc0 srcclkt7 12 45 vddcpu srcclkc7 13 44 gndcpu vddsrc 14 43 cpuclkt1 gndsrc 15 42 cpuclkc1 srcclkt6 16 41 cpuclkt2_itp srcclkc6 17 40 cpuclkc2_itp srcclkt5 18 39 vdd a srcclkc5 19 38 gnda gndsrc 20 37 iref vddsrc 21 36 gndsrc srcclkt4 22 35 vddsrc srcclkc4 23 34 srcclkt0 srcclkt3 24 33 srcclkc0 srcclkc3 25 32 vddati gndsrc 26 31 gndati atigclkt1 27 30 atigclkt0 atigclkc1 28 29 atigclkc0 note: pins preceeded by '**' have a 120 kohm internal pull down resistor pins preceeded by '*' have a 120 kohm internal pull up resistor ICS951411
2 integrated circuit systems, inc. ICS951411 0891e?03/07/05 pin description pin # pin name pin type description 1x1 incr y stal in p ut, nominall y 14.318mhz. 2 x2 out cr y stal out p ut, nominall y 14.318mhz 3 vdd48 pwr power p in for the 48mhz out p ut.3.3v 4 usb_48mhz out 48.00mhz usb clock 5 gnd pwr ground p in. 6 vtt_pwrgd#/pd in vtt_pwrgd# is an active low input used to determine when latched inputs are ready to be sampled. pd is an asynchronous active high input pin used to put the device into a low power state. the internal clocks, plls and the crystal oscillator are sto pp ed. 7 sclk in clock p in of smbus circuitr y , 5v tolerant. 8 sdata i/o data p in for smbus circuitr y , 5v tolerant. 9 **fs_c in fre q uenc y select latch in p ut p in 10 **clkreqa# in output enable for pci express (src) outputs. smbus selects which outputs are controlled. 0 = enabled, 1 = tri-stated 11 **clkreqb# in output enable for pci express (src) outputs. smbus selects which outputs are controlled. 0 = enabled, 1 = tri-stated 12 srcclkt7 out true clock of differential src clock p air. 13 srcclkc7 out com p lement clock of differential src clock p air. 14 vddsrc pwr su pp l y for src clocks, 3.3v nominal 15 gndsrc pwr ground p in for the src out p uts 16 srcclkt6 out true clock of differential src clock p air. 17 srcclkc6 out com p lement clock of differential src clock p air. 18 srcclkt5 out true clock of differential src clock p air. 19 srcclkc5 out com p lement clock of differential src clock p air. 20 gndsrc pwr ground p in for the src out p uts 21 vddsrc pwr su pp l y for src clocks, 3.3v nominal 22 srcclkt4 out true clock of differential src clock p air. 23 srcclkc4 out com p lement clock of differential src clock p air. 24 srcclkt3 out true clock of differential src clock p air. 25 srcclkc3 out com p lement clock of differential src clock p air. 26 gndsrc pwr ground p in for the src out p uts 27 atigclkt1 out true clock of differential src clock p air. 28 atigclkc1 out complementary clock of differential src clock pair.
3 integrated circuit systems, inc. ICS951411 0891e?03/07/05 pin description (continued) pin # pin name pin type description 29 atigclkc0 out com p lementar y clock of differential src clock p air. 30 atigclkt0 out true clock of differential src clock p air. 31 gndati pwr ground for ati gclocks, nominal 3.3v 32 vddati pwr power su pp l y ati gclocks, nominal 3.3v 33 srcclkc0 out com p lement clock of differential src clock p air. 34 srcclkt0 out true clock of differential src clock p air. 35 vddsrc pwr su pp l y for src clocks, 3.3v nominal 36 gndsrc pwr ground p in for the src out p uts 37 iref out this pin establishes the reference cu rrent for the differential current-mode output pairs. this pin requires a fixed pr ecision resistor tied to ground in order to establish the appropriate curr ent. 475 ohms is the standard value. 38 gnda pwr ground p in for the pll core. 39 vdda pwr 3.3v p ower for the pll core. 40 cpuclkc2_itp out complementary clock of differential pai r cpu outputs. these are current mode out p uts. external resistors are re q uired for volta g e bias. 41 cpuclkt2_itp out true clock of differential pair cpu output s. these are current mode outputs. external resistors are re q uired for volta g e bias. 42 cpuclkc1 out complementary clock of differential pai r cpu outputs. these are current mode out p uts. external resistors are re q uired for volta g e bias. 43 cpuclkt1 out true clock of differential pair cpu output s. these are current mode outputs. external resistors are re q uired for volta g e bias. 44 gndcpu pwr ground p in for the cpu out p uts 45 vddcpu pwr su pp l y for cpu clocks, 3.3v nominal 46 cpuclkc0 out complementary clock of differential pai r cpu outputs. these are current mode out p uts. external resistors are re q uired for volta g e bias. 47 cpuclkt0 out true clock of differential pair cpu output s. these are current mode outputs. external resistors are re q uired for volta g e bias. 48 *cpu_stop# in sto p s all cpuclk, exce p t those set to be free runnin g clocks 49 gndpci pwr ground p in for the pci out p uts 50 **ck410#/pciclk0 i/o fs table select latch input pin / 3.3v pci clock output. 0 = ck410 fs table, 1 = ck409 fs table 51 vddpci pwr power su pp l y for pci clocks, nominal 3.3v 52 **test_sel/ref2 i/o test_sel: latched input to select test mode / 14.318 mhz reference clock. 1 = all outputs are ck410 ref/n test mode 0 = all outputs behave normally. 53 **fs_b/ref1 i/o fre q uenc y select latch in p ut p in / 14.318 mhz reference clock. 54 **fs_a/ref0 i/o fre q uenc y select latch in p ut p in / 14.318 mhz reference clock. 55 gnd pwr ground p in. 56 vddref pwr ref, xtal power supply, nominal 3.3v
4 integrated circuit systems, inc. ICS951411 0891e?03/07/05 ICS951411 provides a single-chip clocking solution for the ati rs400-based systems using the latest intel p4 processors. ICS951411 is driven with a 14.318mhz crystal. it generates cpu outputs up to 400mhz and also provides highly accurate src clocks for pci express support. two clock request pins are provided for express-card tm support. general description block diagram power groups main pll pciclk0 control logic xtal osc. cpuclk(2:0) fixed pll usb_48mhz divider dividers ref(2:0) srcclk(7:3,0) clkreqa# s data sclk clkreqb# x1 x2 iref fs(c:a) cpu_stop# vtt_pwrgd#/pd atigclk(1:0) ck410# vdd gnd 56 55 xtal, ref 51 49 pciclk out p ut 45 44 cpuclk out p uts 14, 21, 35 15, 20, 26, 36 srcclk out p uts 32 31 atigclk out p uts 39 38 analo g , cpu pll 3 5 usb_48mhz output pin number description
5 integrated circuit systems, inc. ICS951411 0891e?03/07/05 general smbus serial interface information for the ICS951411 how to write: ? controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) sends the data byte count = x ics clock will acknowledge controller (host) starts sending byte n through byte n + x -1 (see note 2) ics clock will acknowledge each byte one at a time controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) will send a separate start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the data byte count = x ics clock sends byte n + x -1 ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . controller (host) will need to acknowledge each byte controllor (host) will send a not acknowledge bit controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p stop bit x byte index block write operation slave address d2 (h) beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit slave address d3 (h) index block read operation slave address d2 (h) beginning byte = n ack ack data byte count = x ack ics (slave/receiver) controller (host) x byte ack ack
6 integrated circuit systems, inc. ICS951411 0891e?03/07/05 table1: cpu frequency selection table bit 4 cpu fs4 (ck410#) bit 3 cpu fs3 (ss_en) bit2 fsc bit1 fsb bit0 fsa cpu (mhz) pci33 (mhz) spread % 0 0 0 0 0 266.6667 33.3333 0 0 0 0 1 133.3333 33.3333 0 0 0 1 0 200.0000 33.3333 0 0 0 1 1 166.6668 33.3334 0 0 1 0 0 333.3335 33.3334 0 0 1 0 1 100.0000 33.3333 0 0 1 1 0 400.0000 33.3333 00111 0 1 0 0 0 266.6667 33.3333 0 1 0 0 1 133.3333 33.3333 0 1 0 1 0 200.0000 33.3333 0 1 0 1 1 166.6668 33.3334 0 1 1 0 0 333.3335 33.3334 0 1 1 0 1 100.0000 33.3333 0 1 1 1 0 400.0000 33.3333 01111 1 0 0 0 0 100.0000 33.3333 1 0 0 0 1 133.3333 33.3333 1 0 0 1 0 200.0000 33.3333 1 0 0 1 1 166.6668 33.3334 1 0 1 0 0 200.0000 33.3333 1 0 1 0 1 266.6667 33.3333 1 0 1 1 0 400.0000 33.3333 1 0 1 1 1 333.3335 33.3334 1 1 0 0 0 100.0000 33.3333 1 1 0 0 1 133.3333 33.3333 1 1 0 1 0 200.0000 33.3333 1 1 0 1 1 166.6668 33.3334 1 1 1 0 0 200.0000 33.3333 1 1 1 0 1 266.6667 33.3333 1 1 1 1 0 400.0000 33.3333 1 1 1 1 1 333.3335 33.3334 c k 4 1 0 -0.5% no spread -0.5% c k 4 0 9 no spread reserved reserved
7 integrated circuit systems, inc. ICS951411 0891e?03/07/05 src fs4 (ss_en) src fs3 bit2 fs2 bit1 fs1 bit0 fs0 src(7:3,0), atig(1:0) (mhz) spread % src overclock 00000100.00 0 1.00 00001100.00 0 1.00 00010100.00 0 1.00 00011100.00 0 1.00 00100101.00 0 1.01 00101101.00 0 1.01 00110101.00 0 1.01 00111101.00 0 1.01 01000102.00 0 1.02 01001102.00 0 1.02 01010102.00 0 1.02 01011102.00 0 1.02 01100104.00 0 1.04 01101104.00 0 1.04 01110104.00 0 1.04 01111104.00 0 1.04 10000100.00 -0.5% 1.00 10001100.00 -0.5% 1.00 10010100.00 -0.5% 1.00 10011100.00 -0.5% 1.00 10100101.00 -0.5% 1.01 10101101.00 -0.5% 1.01 10110101.00 -0.5% 1.01 10111101.00 -0.5% 1.01 11000102.00 -0.5% 1.02 11001102.00 -0.5% 1.02 11010102.00 -0.5% 1.02 11011102.00 -0.5% 1.02 11100104.00 -0.5% 1.04 11101104.00 -0.5% 1.04 11110104.00 -0.5% 1.04 11111104.00 -0.5% 1.04 table2: src & atig frequency selection table
8 integrated circuit systems, inc. ICS951411 0891e?03/07/05 smbus table: frequency select register pin # name control function t yp e0 1 pwd bit 7 fs source latched input or smbus frequency select rw latched inputs smbus 0 bit 6 ss_en s p read enable rw off on 0 bit 5 reserved reserved rw reserved reserved x bit 4 ck410# cpu freq select bit 4 rw latched bit 3 cpu fs3 cpu ss_en rw 0 bit 2 cpu fs_c cpu fre q select bit 2 rw latched bit 1 cpu fs_b cpu fre q select bit 1 rw latched bit 0 cpu fs_a cpu freq select bit 0 rw latched note: b y te 0 bit 6 and b y te 0 bit 3 must both be '1' to enable s p read for the pci $ cpu clocks. b y te 5 bit 4 must be set to 1 to enable s p read for the src & atigclks. smbus table: output control register pin # name control function t yp e0 1 pwd bit 7 pciclk0 out p ut enable rw disable enable 1 bit 6 cpuclk2 out p ut enable rw disable enable 1 bit 5 usb_48mhz out p ut enable rw disable enable 1 bit 4 ref0 out p ut enable rw disable enable 1 bit 3 ref1 out p ut enable rw disable enable 1 bit 2 ref2 out p ut enable rw disable enable 1 bit 1 cpuclk0 out p ut enable rw disable enable 1 bit 0 cpuclk1 output enable rw disable enable 1 smbus table: clkreqb# output control register pin # name control function t yp e0 1 pwd bit 7 reqbsrc7 clkreqb# controls src7 rw does not control controls 0 bit 6 reqbsrc6 clkreqb# controls src6 rw does not control controls 0 bit 5 reqbsrc5 clkreqb# controls src5 rw does not control controls 0 bit 4 reqbsrc4 clkreqb# controls src4 rw does not control controls 0 bit 3 reqbsrc3 clkreqb# controls src3 rw does not control controls 0 bit 2 reserved reserved rw reserved reserved x bit 1 reserved reserved rw reserved reserved x bit 0 reqbsrc0 clkreqb# controls src0 rw does not control controls 0 note: cpu0_sto p _en ( b y te2, bit 2 ) onl y exists in devices with rev id = 2 or hi g her - 34,33 18,19 22,23 24,25 - 43,42 byte 2 12,13 16,17 54 53 52 47,46 byte 1 50 41,40 4 - see table 1: cpu frequency selection table - - - - byte 0 - - -
9 integrated circuit systems, inc. ICS951411 0891e?03/07/05 smbus table: srcclk(7:3,0), clkreqa# output control register pin # name control function t yp e0 1 pwd bit 7 srcclk7 rw disable enable 1 bit 6 srcclk6 rw disable enable 1 bit 5 srcclk5 rw disable enable 1 bit 4 srcclk4 rw disable enable 1 bit 3 srcclk3 rw disable enable 1 bit 2 srcclk0 r w disable enable 1 bit 1 reqasrc3 clkreqa# controls src3 rw does not control controls 0 bit 0 reqasrc0 clkreqa# controls src0 rw does not control controls 0 smbus table: srcclk(3,0), atigclk output control register pin # name control function t yp e0 1 pwd bit 7 reqasrc7 clkreqa# controls src7 rw does not control controls 0 bit 6 reqasrc6 clkreqa# controls src6 rw does not control controls 0 bit 5 reqasrc5 clkreqa# controls src5 rw does not control controls 0 bit 4 reqasrc4 clkreqa# controls src4 rw does not control controls 0 bit 3 atigclk1 rw disabled enabled 1 bit 2 atigclk0 rw disabled enabled 1 bit 1 differential output disable mode hi-z or driven when disabled rw driven hi-z 0 bit 0 usb_48str 48mhz strength control rw 1x 2x 1 note: do not simultaneously select clkreqa# and clkreqb# to control an src output. behavior of the device is undefined under these conditions. smbus table: output drive and atig frequency control register pin # name control function t yp e0 1 pwd bit 7 ref2str ref2 strength control rw 1x 2x 1 bit 6 cpu2_stop_en r w free-run stoppable 1 bit 5 cpu1_stop_en r w free-run stoppable 1 bit 4 srcfs4 (ss_en) freq select bit 4 (ss_en) rw 0 bit 3 srcfs3 freq select bit 3 rw 0 bit 2 srcfs2 freq select bit 2 rw 0 bit 1 srcfs1 freq select bit 1 rw 0 bit 0 srcfs0 freq select bit 0 rw 0 note: cpu(1:2)_stop_en (byte5, bit 6:5) only exist in devices with rev id = 2 or higher 0 = cpu is free-run 1 = cpu is stopped b y see table 2 src frequency selection - - - - - b y te 5 52 41,40 43,42 output enable these outputs cannot be controlled by clkreq# pins. 30,29 cpu, src, atig 4 16,17 18,19 22,23 27,28 24,25 34,33 b y te 4 12,13 master output control. enables or disables output, regardless of clkreq# inputs. 16,17 18,19 22,23 24,25 34,33 b y te 3 12,13
10 integrated circuit systems, inc. ICS951411 0891e?03/07/05 smbus table: device id register pin # name control function type 0 1 pwd bit 7 devid 7 device id msb r - - 0 bit 6 devid 6 device id 6 r - - 0 bit 5 devid 5 device id 5 r - - 0 bit 4 devid 4 device id4 r - - 1 bit 3 devid 3 device id3 r - - 0 bit 2 devid 2 device id2 r - - 0 bit 1 devid 1 device id1 r - - 1 bit 0 devid 0 device id lsb r - - 1 smbus table: vendor id register pin # name control function type 0 1 pwd bit 7 rid3 r - - x bit 6 rid2 r - - x bit 5 rid1 r - - x bit 4 rid0 r - - x bit 3 vid3 r - - 0 bit 2 vid2 r - - 0 bit 1 vid1 r - - 0 bit 0 vid0 r - - 1 smbus table: byte count register pin # name control function type 0 1 pwd bit 7 bc7 rw 0 bit 6 bc6 rw 0 bit 5 bc5 rw 0 bit 4 bc4 rw 0 bit 3 bc3 rw 1 bit 2 bc2 rw 0 bit 1 bc1 rw 0 bit 0 bc0 rw 1 b y tes 9 throu g h 21 are reserved byte 6 - - - - - - - - byte 8 - - - byte 7 - revision id starts at 0 hex for a revsion. - vendor id (0001 = ics) - - - writing to this register will configure how many bytes will be read back, default is 9 bytes. - - - - - - - - byte count programming b(7:0) test clarification table comments hw test_sel/ref2 hw pin output <0.8v normal >2.0v hi-z 1. power-up w/ test_sel/ref2 > 2.0v to enter test mode. 2. cycle power to disable test mode
11 integrated circuit systems, inc. ICS951411 0891e?03/07/05 absolute max symbol parameter min max units vdd_a 3.3v core supply voltage v dd + 0.5v v vdd_in 3.3v logic input supply voltage gnd - 0.5 v dd + 0.5v v ts storage temperature -65 150 c tambient ambient operating temp 0 70 c tcase case temperature 115 c esd prot input e s d protection human body model 2000 v electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5% parameter symbol conditions min typ max units notes input high voltage v ih 3.3 v +/-5% 2 v dd + 0.3 v1 input low voltage v il 3.3 v +/-5% v ss - 0.3 0.8 v 1 input high current i ih v in = v dd -5 5 ua 1 i il1 v in = 0 v; inputs with no pull-up resistors -5 ua 1 i il2 v in = 0 v; inputs with pull-up resistors -200 ua 1 low threshold input- high voltage v ih_fs 3.3 v +/-5% 0.7 v dd + 0.3 v1 low threshold input- low volta g e v il_fs 3.3 v +/-5% v ss - 0.3 0.35 v 1 operating current i dd3.3op all outputs driven 400 ma 1 all diff p airs driven 70 ma 1 all differential p airs tri-stated 12 ma 1 input frequency f i v dd = 3.3 v 14.31818 mhz 3 pin inductance l pin 7nh1 c in logic inputs 5 pf 1 c out output pin capacitance 6 pf 1 c inx x1 & x2 pins 5 pf 1 clk stabilization t stab from v dd power-up or de- assertion of pd# to 1st clock 1.8 ms 1,2 modulation fre q uenc y trian g ular modulation 30 33 khz 1 tdrive_pd# cpu output enable after pd# de-assertion 300 us 1 tfall_pd# pd# fall time of 5 ns 1 trise_pd# pd# rise time of 5 ns 2 smbus voltage v dd 2.7 5.5 v 1 low-level output voltage v ol @ i pullup 0.4 v 1 current sinking at v ol = 0.4 v i pullup 4ma1 sclk/sdata clock/data rise time t ri2c (max vil - 0.15) to ( min vih + 0.15 ) 1000 ns 1 sclk/sdata clock/data fall time t fi2c (min vih + 0.15) to ( max vil - 0.15 ) 300 ns 1 1 guaranteed b y desi g n and characterization, not 100% tested in p roduction. 2 see timin g dia g rams for timin g re q uirements. pp m fre q uenc y accurac y on pll out p uts. 3 input frequency should be measured at the refout pin and tuned to ideal 14.31818mhz to meet input low current powerdown current i dd3.3pd input capacitance
12 integrated circuit systems, inc. ICS951411 0891e?03/07/05 electrical characteristics - cpu 0.7v current mode differential pair t a = 0 - 70c; v dd = 3.3 v +/-5%; c l =2pf, r s =33.2 ? , r p =49.9 ?, ref = 475? parameter symbol conditions min typ max units notes current source output im p edance zo v o = v x 3000 ? 1 voltage high vhigh 660 850 1,3 voltage low vlow -150 150 1,3 max volta g e vovs 1150 1 min volta g e vuds -300 1 crossin g volta g e ( abs ) vcross ( abs ) 250 550 mv 1 crossing voltage (var) d-vcross variation of crossin g over all ed g es 140 mv 1 lon g accurac y pp msee t p eriod min-max values -300 300 pp m1,2 400mhz nominal 2.4993 2.5008 ns 2 400mhz s p read 2.4993 2.5133 ns 2 333.33mhz nominal 2.9991 3.0009 ns 2 333.33mhz s p read 2.9991 3.016 ns 2 266.66mhz nominal 3.7489 3.7511 ns 2 266.66mhz s p read 3.7489 3.77 ns 2 200mhz nominal 4.9985 5.0015 ns 2 200mhz s p read 4.9985 5.0266 ns 2 166.66mhz nominal 5.9982 6.0018 ns 2 166.66mhz s p read 5.9982 6.0320 ns 2 133.33mhz nominal 7.4978 7.5023 ns 2 133.33mhz s p read 7.4978 7.5400 ns 2 100.00mhz nominal 9.9970 10.0030 ns 2 100.00mhz s p read 9.9970 10.0533 ns 2 400mhz nominal/s p read 2.4143 ns 1,2 333.33mhz nominal/s p read 2.9141 ns 1,2 266.66mhz nominal/s p read 3.6639 ns 1,2 200mhz nominal/s p read 4.8735 ns 1,2 166.66mhz nominal/s p read 5.8732 ns 1,2 133.33mhz nominal/s p read 7.3728 ns 1,2 100.00mhz nominal/s p read 9.8720 ns 1,2 rise time t r v ol = 0.175v, v oh = 0.525v 175 700 ps 1 fall time t f v oh = 0.525v v ol = 0.175v 175 700 ps 1 rise time variation d-t r 125 ps 1 fall time variation d-t f 125 ps 1 duty cycle d t3 measurement from differential wavefrom 45 55 % 1 skew t sk3 cpu(1:0), v t = 50% 100 ps 1 skew t sk4 cpu(1:0) to cpu2_itp, v t = 50% 150 ps 1 jitter, cycle to cycle t jcyc-cyc measurement from differential wavefrom ( cpu2_itp ) 125 ps 1 jitter, cycle to cycle t jcyc-cyc measurement from differential wavefrom, ( cpu ( 1:0 )) 85 ps 1 1 guaranteed b y desi g n and characterization, not 100% tested in p roduction. 2 all lon g term accurac y and clock period s p ecifications are g uaranteed assumin g that refout is at 14.31818mhz 3 i ref = v dd /(3xr r ). for r r = 475 ? (1%), i ref = 2.32ma. i oh = 6 x i ref and v oh = 0.7v @ z o =50 ? . t absmin absolute min period statistical measurement on single ended signal using oscilloscope math function. mv measurement on sin g le ended signal using absolute value. mv average period tperiod
13 integrated circuit systems, inc. ICS951411 0891e?03/07/05 electrical characteristics - src 0.7v current mode differential pair t a = 0 - 70c; v dd = 3.3 v +/-5%; c l =2pf, r s =33.2 ? , r p =49.9 ?, ref = 475? parameter symbol conditions min typ max units notes current source output im p edance zo v o = v x 3000 ? 1 volta g e hi g hvhi g h 660 850 1,3 volta g e low vlow -150 150 1,3 max volta g e vovs 1150 1 min volta g e vuds -300 1 crossing voltage (abs) vcross(abs) 250 350 550 mv 1 crossing voltage (var) d-vcross variation of crossing over all ed g es 12 140 mv 1 long accuracy ppm see tperiod min-max values -300 300 ppm 1,2 100.00mhz nominal 9.9970 10.0030 ns 2 100.00mhz s p read 9.9970 10.0533 ns 2 absolute min period tabsmin 100.00mhz nominal/s p read 9.8720 ns 1,2 rise time t r v ol = 0.175v, v oh = 0.525v 175 700 ps 1 fall time t f v oh = 0.525v v ol = 0.175v 175 700 ps 1 rise time variation d-t r 30 125 ps 1 fall time variation d-t f 30 125 ps 1 duty cycle d t3 measurement from differential wavefrom 45 55 % 1 skew t sk3 v t = 50% 250 ps 1 jitter, cycle to cycle t jcyc-cyc measurement from differential wavefrom 125 ps 1 1 guaranteed b y desi g n and characterization, not 100% tested in p roduction. 2 all lon g term accurac y and clock period s p ecifications are g uaranteed assumin g that refout is at 14.31818mhz 3 i ref = v dd /(3xr r ). for r r = 475 ? (1%), i ref = 2.32ma. i oh = 6 x i ref and v oh = 0.7v @ z o =50 ? . mv measurement on single ended signal using mv average period tperiod statistical measurement on single ended signal
14 integrated circuit systems, inc. ICS951411 0891e?03/07/05 electrical characteristics - pciclk/pciclk_f t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units notes lon g accurac y pp m see t p eriod min-max values -300 300 pp m1,2 33.33mhz out p ut nominal 29.9910 30.0090 ns 2 33.33mhz out p ut s p read 29.9910 30.1598 ns 2 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.55 v 1 v oh @min = 1.0 v -33 ma 1 v oh @ max = 3.135 v -33 ma 1 v ol @ min = 1.95 v 30 ma 1 v ol @ max = 0.4 v 38 ma 1 edge rate rising edge rate 1 4 v/ns 1 ed g e rate fallin g ed g e rate 1 4 v/ns 1 rise time t r1 v ol = 0.4 v, v oh = 2.4 v 0.5 2 ns 1 fall time t f1 v oh = 2.4 v, v ol = 0.4 v 0.5 2 ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 jitter t jcyc-cyc v t = 1.5 v 250 ps 1 1 guaranteed b y desi g n and characterization, not 100% tested in p roduction. 2 all lon g term accurac y and clock period s p ecifications are g uaranteed assumin g that refout is at 14.31818mhz output low current i ol clock period t period output high current i oh electrical characteristics - 48mhz, usb t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units notes lon g accurac y pp msee t p eriod min-max values -100 100 pp m1,2 clock p eriod t p eriod 48.00mhz out p ut nominal 20.8313 20.8354 ns 2 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.55 v 1 v oh @ min = 1.0 v -33 ma 1 v oh @ max = 3.135 v -33 ma 1 v ol @min = 1.95 v 30 ma 1 v ol @ max = 0.4 v 38 ma 1 ed g e rate risin g ed g e rate 1 2 v/ns 1 edge rate falling edge rate 1 2 v/ns 1 rise time t r1 v ol = 0.4 v, v oh = 2.4 v 12ns1 fall time t f1 v oh = 2.4 v, v ol = 0.4 v 12ns1 duty cycle d t1 v t = 1.5 v 45 55 % 1 jitter, cycle to cycle t jcyc-cyc v t = 1.5 v 175 ps 1 1 guaranteed b y desi g n and characterization, not 100% tested in p roduction. 2 all lon g term accurac y and clock period s p ecifications are g uaranteed assumin g that refout is at 14.31818mhz output low current i ol output high current i oh
15 integrated circuit systems, inc. ICS951411 0891e?03/07/05 electrical characteristics - ref-14.318mhz t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units notes lon g accurac y pp m see t p eriod min-max values -300 300 pp m1 clock period t period 14.318mhz output nominal 69.8270 69.8550 ns 1 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 output high current i oh v oh @min = 1.0 v, v oh @max = 3.135 v -29 -23 ma 1 output low current i ol v ol @min = 1.95 v, v ol @max = 0.4 v 29 27 ma 1 rise time t r1 v ol = 0.4 v, v oh = 2.4 v 12ns1 fall time t f1 v oh = 2.4 v, v ol = 0.4 v 12ns1,2 skew t sk1 v t = 1.5 v 500 ps 2 duty cycle d t1 v t = 1.5 v 45 55 % 1,2 jitter t jcyc-cyc v t = 1.5 v 1000 ps 1 1 guaranteed b y desi g n and characterization, not 100% tested in p roduction. 2 all lon g term accurac y and clock period s p ecifications are g uaranteed assumin g that refout is at 14.31818mhz
16 integrated circuit systems, inc. ICS951411 0891e?03/07/05 src reference clock common recommendations for differential routing dimension or value unit figure l1 length, route as non -coupled 50 ohm trace. 0.5 max inch 2, 3 l2 length, route as non -coupled 50 ohm trace. 0.2 max inch 2, 3 l3 length, route as non -coupled 50 ohm trace. 0.2 max inch 2, 3 rs 33 ohm 2, 3 rt 49.9 ohm 2, 3 down device differential routing dimension or value unit figure l4 length, route as coupled microstrip 100 ohm differential trace. 2 min to 16 max inch 2 l4 length, route as coup led stripline 100 ohm differential trace. 1.8 min to 14.4 max inch 2 differential routing to pci express connector dimension or value unit figure l4 length, route as coupled microstrip 100 ohm differential trace. 0.25 to 14 max inch 3 l4 length, rout e as coupled stripline 100 ohm differential trace. 0.225 min to 12.6 max inch 3 fig.1 rs rs rt rt hscl output buffer pci ex ref_clk test load l1 l2 l3? l4 l1? l2? l3 l4? fig.2 rs rs rt rt hscl output buffer pci ex board down device ref_clk input l1 l2 l3? l4 l1? l2? l3 l4? fig.3 rs rs rt rt hscl output buffer pci ex add in board ref_clk input l1 l2 l3? l4 l1? l2? l3 l4?
17 integrated circuit systems, inc. ICS951411 0891e?03/07/05 fig. 1 shared pin operation - input/output pins the i/o pins designated by (input/output) on the ics951416 serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. at the end of power-on reset, (see ac characteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm (10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. via to vdd clock trace to load series term. res. programming header via to gnd device pad 2k 8.2k figure 1 shows a means of implementing this function when a switch or 2 pin header is used. with no jumper is installed the pin will be pulled high. with the jumper in place the pin will be pulled low. if programmability is not necessary, than only a single resistor is necessary. the programming resistors should be located close to the series termination resistor to minimize the current loop area. it is more important to locate the series termination resistor close to the driver than the programming resistor.
18 integrated circuit systems, inc. ICS951411 0891e?03/07/05 min max min max a 2.41 2.80 .095 .110 a1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010 d e 10.03 10.68 .395 .420 e1 7.40 7.60 .291 .299 e h 0.38 0.64 .015 .025 l 0.50 1.02 .020 .040 n a0808 variations min max min max 56 18.31 18.55 .720 .730 10-0034 0.635 basic 0.025 basic common dimensions in millimeters in inches common dimensions reference doc.: jedec publication 95, mo-118 56-lead, 300 mil body, 25 mil, ssop n see variations see variations d mm. d (inch) symbol see variations see variations index area index area 12 1 2 n d h x 45 h x 45 e1 e seating plane seating plane a1 a e -c- - c - b .10 (.004) c .10 (.004) c c l ordering information ICS951411 y flft example: designation for tape and reel packaging annealed lead free (optional) package type f = ssop revision designator (will not correlate with datasheet revision) device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device ics xxxx y f lf t
19 integrated circuit systems, inc. ICS951411 0891e?03/07/05 in d ex a r ea in d ex a r ea 1 2 1 2 n d e1 e s eatin g p lane s eatin g p lane a1 a a 2 a 2 e - c - - c - b c l aaa c min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 d e e1 6.00 6.20 .236 .244 e l 0.45 0.75 .018 .030 n a0808 aaa -- 0.10 -- .004 variations min max min max 56 13.90 14.10 .547 .555 10-0039 56-lead 6.10 mm. bod y , 0.50 mm. pitch tssop ( 240 mil ) ( 20 mil ) symbol in millimeters in inches common dimensions common dimensions see variations see variations 8.10 basic 0.319 basic 0.50 basic 0.020 basic see variations see variations n d mm. d (inch) reference doc.: jedec publication 95, m o-153 ordering information ICS951411 y glft example: designation for tape and reel packaging annealed lead free (optional) package type g = tssop revision designator (will not correlate with datasheet revision) device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device ics xxxx y g lf t

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